Register Files (RF) are multi-port static memories with dedicated READ and WRITE ports for high bandwidth memory operations. The Register Files are important components in today’s devices like Central Processing Unit (CPU) and Network Routers. Low power and area critical RF memories use SRAMs rather than the latches/flip-flops as the building block. Due to lack of performance and short channel effects, scaling of conventional MOSFETs towards Deep Submicron (DSM) dimensions in memories as well as in other System-on-Chip (SoC) designs became tedious.
Recently in DSM designs, the conventional planar MOSFETs are being replaced by thin body FinFETs because of their better subthreshold swing, reduced short channel effects and better scalability. This paper proposes a 6T subthreshold 1R-2W SRAM and 8T 2R-2W SRAM bit cell designs using 25nm FinFET transistors having independent READ and WRITE ports. The proposed structures are with reduced leakage power and also show improved read stability and write stability as compared to the conventional single port SRAM structure.