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A Low-Error, Cost-Efficient Design Procedure for Evaluating Logarithms to be Used in a Logarithmic Arithmetic Processor

Based on an error-flattened, non-uniform-region linear-approximation algorithm, this brief proposes a low-error and a cost-efficient design procedure for realizing an optimized shift-and-add Logarithmic Unit (LU), which uses minimum hardware to meet the desired error constraint for embedded graphics systems. Mathematically, this brief first derives two solutions of the error-flattened algorithm. Subsequently, for an error constraint, the minimum number of approximation regions, n, the corresponding i-th interpolation coefficients (ai, bi), and the regional endpoints (xi-1, xi), 1 ??? i ??? n, are obtained accordingly. Using the unique properties of the logarithmic function, spacing of xi is non-uniform to make errors in each region consistent. Carefully examining the cost of the applied add/subnetwork, a low-cost candidate for a shift-and-add LU is determined. Next, a cost exploration process, which gradually increases n, is performed.

A large number of regions results in a more accurate conversion algorithm that might tolerate more implementation errors by using simple hardware whose cost is lower than that of the inferior candidate. After exploring the cost based on error tolerance, the proposed design procedure finally generates a hardware to meet the desired error constraint. Slightly modifying the regional endpoint xi increases hardware efficiency at the cost of increased error. Proposed circuits were synthesized in UMC 65RVT CMOS technology. Compared to state-of-the-art shift-andadd logarithmic converters, simulation results reveal that the proposed design saves approximately 12.7%–51.1% area of polynomial approximation and improves approximately 1–14-dB SNR gain while achieving a tighter error constraint.

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