In this paper we present a CMOS implementation of a 512×512-cell Associative Content Addressable Memory (ACAM) in 180 nm CMOS. The memory can be operated either as an associative CAM or it can be configured into a Willshaw memory for operating with sparse data. The vector matching operation can use a tunable hit threshold or the strongest hit can be selected with a winner-take-all (WTA) network.
Built-in row and column circuitry can perform logic operations on the contents of the row and column memories. The operation of the circuit is verified experimentally with an example on computing with random vectors.