This paper describes the circuit design and measured performance of a 6-bit 8-GS/s current-steering DAC. A CML interface supporting the maximum conversion rate of 8Gbps is integrated in the chip. A PRBS-7 generator is built in the chip for synchronization as well as for data descrambling.
In order to realize good linearity performance, a 2-2-2 segmental architecture is proposed for optimizing the performance. Measured DNL and INL are within +0.04/-0.12 LSB and +0.11/-0.11 LSB respectively. SFDR is above 37dBc over the Nyquist bandwidth at the sampling rate of 8 GS/s. The chip measures 1420 ×1405 um2.